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[Other resource] mult8x8

Description: 一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
Platform: | Size: 17491 | Author: 胡东 | Hits:

[VHDL-FPGA-Verilog] Lab20

Description: the booth algorithm to implement the 32bits multiplication.-the booth algorithm to implement the 32bit 's multiplication.
Platform: | Size: 56320 | Author: 王琪 | Hits:

[VHDL-FPGA-Verilog] mult_8b_for

Description: 本实验使用Verilog语言 通过FOR循环完成8bit乘法器功能，通过ISE仿真测试，可实现综合-Verilog language used in this experiment through the FOR cycle completed 8bit multiplier function, through the ISE simulation tests can be integrated
Platform: | Size: 205824 | Author: jennycomeon | Hits:

[Other] mul64

Description: 64位乘法器设计实验是我在科大的第一个课程设计，verilog程序的熟练掌握对于微电子专业的学生来讲是非常必要的，对于此次设计我也花费了很长时间。 本设计分为3个部分，即控制和（1）状态选择部分，（2）乘法器部分，（3）加法器部分。 以下我将按此顺序进行说明。需要指出的是，在实际设计中的顺序恰好是颠倒的，这与设计思路有关，在刚开始的时候由于对整体没有一个很好的把握就先选择最简单的一部分几加法器开始入手，然后就是乘法器，最后作乐一个状态控制电路将两部分联系起来。 -A 64-bit multiplier design an experiment at HKUST my first course design, verilog program for microelectronics professional proficiency in terms of students is necessary for the design and I spend a lot of time. The design is divided into three parts, namely, control, and (1) state to select some, (2) multiplier section, and (3) adder part. Click here to order the following I will explain. Be noted that, in the order of the actual design is exactly reversed, which design ideas related to time because at the beginning of a whole does not have a good grasp on the first selection of the most simple part of the beginning of several adder start, and then is the multiplier, the last merry a state control circuit to link the two parts.
Platform: | Size: 1024 | Author: 杨阳 | Hits:

[VHDL-FPGA-Verilog] mul_ser12

Description: 本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。-The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.
Platform: | Size: 305152 | Author: Aaran | Hits:

[VHDL-FPGA-Verilog] mltiply_machine

Description: verilog语言写的乘法器，每一步经过验证，毫发无损，拿出来与大家共享，在quartus II 上编程，仿真在cyclone 2上！！谢谢！-written multiplier verilog language, every step of the proven, intact, and show to share the quartus II on programming, simulation in cyclone 2 on! ! Thank you!
Platform: | Size: 228352 | Author: 谷向前 | Hits:

[VHDL-FPGA-Verilog] MULTIPLE_CORE

Description: 硬件乘法器，其基础就是加法器结构，它已经是现代计算机中必不可少的一部分。[1]乘法器的模型就是基于“移位和相加”的算法。在该算法中，乘法器中每一个比特位都会产生一个局部乘积。第一个局部乘积由乘法器的LSB产生，第二个乘积由乘法器的第二位产生，以此类推。如果相应的乘数比特位是1，那么局部乘积就是被乘数的值，如果相应的乘数比特位是0，那么局部乘积全为0。每次局部乘积都向左移动一位。 -64-bit multiplier design experiment is the first in the HKUST and curriculum design, verilog program for proficiency in students in terms of Microelectronics is necessary for the design I have spent a long time.
Platform: | Size: 26624 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] robust_fir_latest.tar

Description: RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).-RobustVerilog generic FIR filter In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)). The filter can be built according to 3 different architectures, parallel, serial or something in the middle (named Nserial). The architecture is determined according to the MACNUM parameter (multiplayer-accumulator). The RobustVerilog top source file is fir.v. The command line calls it with an additional definition file named def_fir_top.txt The default definition file def_fir_top.txt generates 3 filters, 1 parallel, 1 serial and 1 Nserial. Changing the interconnect parameters should be made only in def_fir_top.txt in the src/base directory (changing multiplier number, filter order etc.).
Platform: | Size: 6144 | Author: 尤恺元 | Hits:

[VHDL-FPGA-Verilog] -Elliptic

Description: We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
Platform: | Size: 116736 | Author: 陳曉慧 | Hits:

[VHDL-FPGA-Verilog] mul1617

Description: 采用verilog RTL级语言，实现了有符号的16位乘17位的乘法器。特点是：采用流水的结构，可以在一个周期内处理完数据。通过QuartusII和Modulesim的功能仿真和时序仿真，并得到正确结果。-Realize the signs of 16 of the 17 patients take on time-multiplier. Features are: the structure of water, can be in a cycle processes the data. Through the QuartusII and Modulesim function simulation and timing simulation, and get the right result.
Platform: | Size: 1024 | Author: 李小白 | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
Platform: | Size: 8192 | Author: Brandon | Hits:

[VHDL-FPGA-Verilog] develop_frame_find

Description: 基于FPGA中OFDM中的帧检测，由于采用简化算法，采用较少的复数乘法器，易于硬件实现，且节省资源，采用verilog实现.-Frame detection based on FPGA for OFDM, a simplified algorithm, using less complex multiplier, easily implemented in hardware, and save resources, the SNR performance is slightly lower than the previous algorithm, but very practical.
Platform: | Size: 320512 | Author: | Hits:

[Other] Low-Error-and-Hardware-Efficient-Fixed-Width-Mult

Description: VERILOG Code for IEEE Paper Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error Run by ModelSim 6.2 software Here paper output and modified paper output can be provided. Phase-1 folder consists of paper output High speed msb multiplication. In phase-2 folder consists of slight change before the multiplication process check the if the multiplication result will give msb or not , if it s possible continue multiplication process otherwise zero can be put on the result.
Platform: | Size: 783360 | Author: anandg | Hits:

[Program doc] latch

Description: Abstract—Power is becoming a precious resource in modern VLSI design, even more so than area. This paper proposes a novel architecture for modular, scalable &reusable hybrid constant co-efficient multiplier (KCM) circuit. Comparison is made between of kcm and multiplier. The implementation results show a significant improvement in performance in terms of area, power & timing. In This paper, we propose to design an 8-point FFT using kcm instead of complex multiplier and multiplier. Here our goal is to implement Radix-2 8-point FFT in hardware using hardware language (verilog) here time constraint is measured with the help of Xilinx FPGA (Field Programmable Gate Array).
Platform: | Size: 560128 | Author: Bahu | Hits:

[VHDL-FPGA-Verilog] cfq8

Description: 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
Platform: | Size: 1024 | Author: 刘杨 | Hits:

[VHDL-FPGA-Verilog] ad5544

Description: 模数乘法器AD5544的Verilog源程序，已在项目中验证了其可行。-Verilog source AD5544 analog multiplier, and have verified its feasibility in the project.
Platform: | Size: 1024 | Author: avion | Hits:

[Other] streamline_div

Description: 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
Platform: | Size: 1024 | Author: Andy Zhou | Hits:

[VHDL-FPGA-Verilog] TX_RX

Description: FPGA用verilog实现串口和电脑的字符串以及单字符精准无误通信，即通过电脑向FPGA发送任一长度数据，FPGA返回PC相同的数据。波特率为9600，本例程为了得到精准的波特率使用了50M时钟的3倍频，测试可用，如有不明的地方，可以给我留言-FPGA implementation using verilog string and the computer serial port and single-character accurate communication, 9600, FPGA using verilog to achieve serial and single-character strings, and the computer communicate accurate and correct, that is, through the computer to the FPGA send any length data, FPGA return PC the same data. 9600 of the routine in order to get accurate baud using a 50M clock multiplier 3, the test can be used, if unknown place, you can give me a message
Platform: | Size: 3475456 | Author: 冷酷豪迈 | Hits:
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